Synthesis-Specific Verification

Overview To build robust, reliable autonomous systems, we have been developing the CIRCA approach to real-time intelligent control. Our goal is to give a CIRCAcontrolled autonomous system models of what it can do, what its goals are, and what the environment can do. From those models, we want CIRCA to automatically generate and execute hard-real-time controllers that are guaranteed to avoid failure and achieve the system’s goals whenever possible. A key component of our approach is the integration of formal verification into the synthesis process. We use formal verification to ensure that the controllers CIRCA builds are guaranteed to avoid system failure states. This abstract briefly describes the current status of our verification system, and the motivation for a set of improvements we are making to form a new verifier system (the Synthesis-Specific Verifier (SSV)) specialized to the controller synthesis process.